//=====================================================================
//
// cinstset.c - 
//
// NOTE:
// for more information, please see the readme file.
//
//=====================================================================
#include "cinstset.h"

#ifdef _MSC_VER
#pragma warning(disable: 4996)
#endif

CInstSyntax cinstruction_set[] = 
{
	/*
		Encoding syntax:
		----------------
		+r Add register value to opcode
		/# Value for Mod R/M register field encoding
		/r Effective address encoding
		ib Byte immediate
		iw Word immediate
		id Dword immediate
		-b Byte relative address
		-i Word or dword relative address
		p0 LOCK instruction prefix (F0h)
		p2 REPNE/REPNZ instruction prefix (F2h)
		p3 REP/REPE/REPZ instruction prefix (F3h) (also SSE prefix)
		po Offset override prefix (66h)
		pa Address override prefix (67h)
	*/

	{"AAA",			"",							"37",				CT_CPU_8086},
	{"AAS",			"",							"3F",				CT_CPU_8086},
	{"AAD",			"",							"D5 0A",			CT_CPU_8086},
	{"AAD",			"imm",						"D5 ib",			CT_CPU_8086},
	{"AAM",			"",							"D4 0A",			CT_CPU_8086},
	{"AAM",			"imm",						"D4 ib",			CT_CPU_8086},
	{"ADC",			"r/m8,reg8",				"10 /r",			CT_CPU_8086},
	{"ADC",			"r/m16,reg16",				"po 11 /r",			CT_CPU_8086},
	{"ADC",			"r/m32,reg32",				"po 11 /r",			CT_CPU_386},
	{"ADC",			"reg8,r/m8",				"12 /r",			CT_CPU_8086},
	{"ADC",			"reg16,r/m16",				"po 13 /r",			CT_CPU_8086},
	{"ADC",			"reg32,r/m32",				"po 13 /r",			CT_CPU_386},
	{"ADC",			"r/m8,imm8",				"80 /2 ib",			CT_CPU_8086},
	{"ADC",			"r/m16,imm16",				"po 81 /2 iw",		CT_CPU_8086},
	{"ADC",			"r/m32,imm32",				"po 81 /2 id",		CT_CPU_386},
	{"ADC",			"r/m16,imm8",				"po 83 /2 ib",		CT_CPU_8086},
	{"ADC",			"r/m32,imm8",				"po 83 /2 ib",		CT_CPU_386},
	{"ADC",			"AL,imm8",					"14 ib",			CT_CPU_8086},
	{"ADC",			"AX,imm16",					"po 15 iw",			CT_CPU_8086},
	{"ADC",			"EAX,imm32",				"po 15 id",			CT_CPU_386},
	{"ADD",			"r/m8,reg8",				"00 /r",			CT_CPU_8086},
	{"ADD",			"r/m16,reg16",				"po 01 /r",			CT_CPU_8086},
	{"ADD",			"r/m32,reg32",				"po 01 /r",			CT_CPU_386},
	{"ADD",			"reg8,r/m8",				"02 /r",			CT_CPU_8086},
	{"ADD",			"reg16,r/m16",				"po 03 /r",			CT_CPU_8086},
	{"ADD",			"reg32,r/m32",				"po 03 /r",			CT_CPU_386},
	{"ADD",			"r/m8,imm8",				"80 /0 ib",			CT_CPU_8086},
	{"ADD",			"r/m16,imm16",				"po 81 /0 iw",		CT_CPU_8086},
	{"ADD",			"r/m32,imm32",				"po 81 /0 id",		CT_CPU_386},
	{"ADD",			"r/m16,imm8",				"po 83 /0 ib",		CT_CPU_8086},
	{"ADD",			"r/m32,imm8",				"po 83 /0 ib",		CT_CPU_386},
	{"ADD",			"AL,imm8",					"04 ib",			CT_CPU_8086},
	{"ADD",			"AX,imm16",					"po 05 iw",			CT_CPU_8086},
	{"ADD",			"EAX,imm32",				"po 05 id",			CT_CPU_386},
	{"ADDPS",		"xmmreg,r/m128",			"0F 58 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"ADDSS",		"xmmreg,xmmreg/mem32",		"p3 0F 58 /r",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"AND",			"r/m8,reg8",				"20 /r",			CT_CPU_8086},
	{"AND",			"r/m16,reg16",				"po 21 /r",			CT_CPU_8086},
	{"AND",			"r/m32,reg32",				"po 21 /r",			CT_CPU_386},
	{"AND",			"reg8,r/m8",				"22 /r",			CT_CPU_8086},
	{"AND",			"reg16,r/m16",				"po 23 /r",			CT_CPU_8086},
	{"AND",			"reg32,r/m32",				"po 23 /r",			CT_CPU_386},
	{"AND",			"r/m8,imm8",				"80 /4 ib",			CT_CPU_8086},
	{"AND",			"r/m16,imm16",				"po 81 /4 iw",		CT_CPU_8086},
	{"AND",			"r/m32,imm32",				"po 81 /4 id",		CT_CPU_386},
	{"AND",			"r/m16,imm8",				"po 83 /4 ib",		CT_CPU_8086},
	{"AND",			"r/m32,imm8",				"po 83 /4 ib",		CT_CPU_386},
	{"AND",			"AL,imm8",					"24 ib",			CT_CPU_8086},
	{"AND",			"AX,imm16",					"po 25 iw",			CT_CPU_8086},
	{"AND",			"EAX,imm32",				"po 25 id",			CT_CPU_386},
	{"ANDNPS",		"xmmreg,r/m128",			"0F 55 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"ANDPS",		"xmmreg,r/m128",			"0F 54 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
//	{"ARPL",		"r/m16,reg16",				"63 /r",			CT_CPU_286 | CT_CPU_PRIV},
	{"BOUND",		"reg16,mem",				"po 62 /r",			CT_CPU_186},
	{"BOUND",		"reg32,mem",				"po 62 /r",			CT_CPU_386},
	{"BSF",			"reg16,r/m16",				"po 0F BC /r",		CT_CPU_386},
	{"BSF",			"reg32,r/m32",				"po 0F BC /r",		CT_CPU_386},
	{"BSR",			"reg16,r/m16",				"po 0F BD /r",		CT_CPU_386},
	{"BSR",			"reg32,r/m32",				"po 0F BD /r",		CT_CPU_386},
	{"BSWAP",		"reg32",					"po 0F C8 +r",		CT_CPU_486},
	{"BT",			"r/m16,reg16",				"po 0F A3 /r",		CT_CPU_386},
	{"BT",			"r/m32,reg32",				"po 0F A3 /r",		CT_CPU_386},
	{"BT",			"r/m16,imm8",				"po 0F BA /4 ib",	CT_CPU_386},
	{"BT",			"r/m32,imm8",				"po 0F BA /4 ib",	CT_CPU_386},
	{"BTC",			"r/m16,reg16",				"po 0F BB /r",		CT_CPU_386},
	{"BTC",			"r/m32,reg32",				"po 0F BB /r",		CT_CPU_386},
	{"BTC",			"r/m16,imm8",				"po 0F BA /7 ib",	CT_CPU_386},
	{"BTC",			"r/m32,imm8",				"po 0F BA /7 ib",	CT_CPU_386},
	{"BTR",			"r/m16,reg16",				"po 0F B3 /r",		CT_CPU_386},
	{"BTR",			"r/m32,reg32",				"po 0F B3 /r",		CT_CPU_386},
	{"BTR",			"r/m16,imm8",				"po 0F BA /6 ib",	CT_CPU_386},
	{"BTR",			"r/m32,imm8",				"po 0F BA /6 ib",	CT_CPU_386},
	{"BTS",			"r/m16,reg16",				"po 0F AB /r",		CT_CPU_386},
	{"BTS",			"r/m32,reg32",				"po 0F AB /r",		CT_CPU_386},
	{"BTS",			"r/m16,imm",				"po 0F BA /5 ib",	CT_CPU_386},
	{"BTS",			"r/m32,imm",				"po 0F BA /5 ib",	CT_CPU_386},
	{"CALL",		"imm",						"E8 -i",			CT_CPU_8086},
//	{"CALL",		"imm:imm16",				"po 9A iw iw",		CT_CPU_8086},
//	{"CALL",		"imm:imm32",				"po 9A id iw",		CT_CPU_386},
//	{"CALL",		"FAR mem16",				"po FF /3",			CT_CPU_8086},
//	{"CALL",		"FAR mem32",				"po FF /3",			CT_CPU_386},
	{"CALL",		"WORD r/m16",				"po FF /2",			CT_CPU_8086},
	{"CALL",		"DWORD r/m32",				"po FF /2",			CT_CPU_386},
	{"CBW",			"",							"po 98",			CT_CPU_8086},
	{"CWD",			"",							"po 99",			CT_CPU_8086},
	{"CDQ",			"",							"po 99",			CT_CPU_386},
	{"CWDE",		"",							"po 98",			CT_CPU_386},
	{"CLC",			"",							"F8",				CT_CPU_8086},
	{"CLD",			"",							"FC",				CT_CPU_8086},
	{"CLI",			"",							"FA",				CT_CPU_8086},
//	{"CLTS",		"",							"0F 06",			CT_CPU_286 | CT_CPU_PRIV},
	{"CMC",			"",							"F5",				CT_CPU_8086},
	{"CMOVO",		"reg16,r/m16",				"po 0F 40 /r",		CT_CPU_P6},
	{"CMOVNO",		"reg16,r/m16",				"po 0F 41 /r",		CT_CPU_P6},
	{"CMOVB",		"reg16,r/m16",				"po 0F 42 /r",		CT_CPU_P6},
	{"CMOVC",		"reg16,r/m16",				"po 0F 42 /r",		CT_CPU_P6},
	{"CMOVNEA",		"reg16,r/m16",				"po 0F 42 /r",		CT_CPU_P6},
	{"CMOVAE",		"reg16,r/m16",				"po 0F 43 /r",		CT_CPU_P6},
	{"CMOVNB",		"reg16,r/m16",				"po 0F 43 /r",		CT_CPU_P6},
	{"CMOVNC",		"reg16,r/m16",				"po 0F 43 /r",		CT_CPU_P6},
	{"CMOVE",		"reg16,r/m16",				"po 0F 44 /r",		CT_CPU_P6},
	{"CMOVZ",		"reg16,r/m16",				"po 0F 44 /r",		CT_CPU_P6},
	{"CMOVNE",		"reg16,r/m16",				"po 0F 45 /r",		CT_CPU_P6},
	{"CMOVNZ",		"reg16,r/m16",				"po 0F 45 /r",		CT_CPU_P6},
	{"CMOVBE",		"reg16,r/m16",				"po 0F 46 /r",		CT_CPU_P6},
	{"CMOVNA",		"reg16,r/m16",				"po 0F 46 /r",		CT_CPU_P6},
	{"CMOVA",		"reg16,r/m16",				"po 0F 47 /r",		CT_CPU_P6},
	{"CMOVNBE",		"reg16,r/m16",				"po 0F 47 /r",		CT_CPU_P6},
	{"CMOVS",		"reg16,r/m16",				"po 0F 48 /r",		CT_CPU_P6},
	{"CMOVNS",		"reg16,r/m16",				"po 0F 49 /r",		CT_CPU_P6},
	{"CMOVP",		"reg16,r/m16",				"po 0F 4A /r",		CT_CPU_P6},
	{"CMOVPE",		"reg16,r/m16",				"po 0F 4A /r",		CT_CPU_P6},
	{"CMOVNP",		"reg16,r/m16",				"po 0F 4B /r",		CT_CPU_P6},
	{"CMOVPO",		"reg16,r/m16",				"po 0F 4B /r",		CT_CPU_P6},
	{"CMOVL",		"reg16,r/m16",				"po 0F 4C /r",		CT_CPU_P6},
	{"CMOVNGE",		"reg16,r/m16",				"po 0F 4C /r",		CT_CPU_P6},
	{"CMOVGE",		"reg16,r/m16",				"po 0F 4D /r",		CT_CPU_P6},
	{"CMOVNL",		"reg16,r/m16",				"po 0F 4D /r",		CT_CPU_P6},
	{"CMOVLE",		"reg16,r/m16",				"po 0F 4E /r",		CT_CPU_P6},
	{"CMOVNG",		"reg16,r/m16",				"po 0F 4E /r",		CT_CPU_P6},
	{"CMOVG",		"reg16,r/m16",				"po 0F 4F /r",		CT_CPU_P6},
	{"CMOVNLE",		"reg16,r/m16",				"po 0F 4F /r",		CT_CPU_P6},
	{"CMOVO",		"reg32,r/m32",				"po 0F 40 /r",		CT_CPU_P6},
	{"CMOVNO",		"reg32,r/m32",				"po 0F 41 /r",		CT_CPU_P6},
	{"CMOVB",		"reg32,r/m32",				"po 0F 42 /r",		CT_CPU_P6},
	{"CMOVC",		"reg32,r/m32",				"po 0F 42 /r",		CT_CPU_P6},
	{"CMOVNEA",		"reg32,r/m32",				"po 0F 42 /r",		CT_CPU_P6},
	{"CMOVAE",		"reg32,r/m32",				"po 0F 43 /r",		CT_CPU_P6},
	{"CMOVNB",		"reg32,r/m32",				"po 0F 43 /r",		CT_CPU_P6},
	{"CMOVNC",		"reg32,r/m32",				"po 0F 43 /r",		CT_CPU_P6},
	{"CMOVE",		"reg32,r/m32",				"po 0F 44 /r",		CT_CPU_P6},
	{"CMOVZ",		"reg32,r/m32",				"po 0F 44 /r",		CT_CPU_P6},
	{"CMOVNE",		"reg32,r/m32",				"po 0F 45 /r",		CT_CPU_P6},
	{"CMOVNZ",		"reg32,r/m32",				"po 0F 45 /r",		CT_CPU_P6},
	{"CMOVBE",		"reg32,r/m32",				"po 0F 46 /r",		CT_CPU_P6},
	{"CMOVNA",		"reg32,r/m32",				"po 0F 46 /r",		CT_CPU_P6},
	{"CMOVA",		"reg32,r/m32",				"po 0F 47 /r",		CT_CPU_P6},
	{"CMOVNBE",		"reg32,r/m32",				"po 0F 47 /r",		CT_CPU_P6},
	{"CMOVS",		"reg32,r/m32",				"po 0F 48 /r",		CT_CPU_P6},
	{"CMOVNS",		"reg32,r/m32",				"po 0F 49 /r",		CT_CPU_P6},
	{"CMOVP",		"reg32,r/m32",				"po 0F 4A /r",		CT_CPU_P6},
	{"CMOVPE",		"reg32,r/m32",				"po 0F 4A /r",		CT_CPU_P6},
	{"CMOVNP",		"reg32,r/m32",				"po 0F 4B /r",		CT_CPU_P6},
	{"CMOVPO",		"reg32,r/m32",				"po 0F 4B /r",		CT_CPU_P6},
	{"CMOVL",		"reg32,r/m32",				"po 0F 4C /r",		CT_CPU_P6},
	{"CMOVNGE",		"reg32,r/m32",				"po 0F 4C /r",		CT_CPU_P6},
	{"CMOVGE",		"reg32,r/m32",				"po 0F 4D /r",		CT_CPU_P6},
	{"CMOVNL",		"reg32,r/m32",				"po 0F 4D /r",		CT_CPU_P6},
	{"CMOVLE",		"reg32,r/m32",				"po 0F 4E /r",		CT_CPU_P6},
	{"CMOVNG",		"reg32,r/m32",				"po 0F 4E /r",		CT_CPU_P6},
	{"CMOVG",		"reg32,r/m32",				"po 0F 4F /r",		CT_CPU_P6},
	{"CMOVNLE",		"reg32,r/m32",				"po 0F 4F /r",		CT_CPU_P6},
	{"CMP",			"r/m8,reg8",				"38 /r",			CT_CPU_8086},
	{"CMP",			"r/m16,reg16",				"po 39 /r",			CT_CPU_8086},
	{"CMP",			"r/m32,reg32",				"po 39 /r",			CT_CPU_386},
	{"CMP",			"reg8,r/m8",				"3A /r",			CT_CPU_8086},
	{"CMP",			"reg16,r/m16",				"po 3B /r",			CT_CPU_8086},
	{"CMP",			"reg32,r/m32",				"po 3B /r",			CT_CPU_386},
	{"CMP",			"r/m8,imm8",				"80 /7 ib",			CT_CPU_8086},
	{"CMP",			"r/m16,imm16",				"po 81 /7 iw",		CT_CPU_8086},
	{"CMP",			"r/m32,imm32",				"po 81 /7 id",		CT_CPU_386},
	{"CMP",			"r/m16,imm8",				"po 83 /7 ib",		CT_CPU_8086},
	{"CMP",			"r/m32,imm8",				"po 83 /7 ib",		CT_CPU_386},
	{"CMP",			"AL,imm8",					"3C ib",			CT_CPU_8086},
	{"CMP",			"AX,imm16",					"po 3D iw",			CT_CPU_8086},
	{"CMP",			"EAX,imm32",				"po 3D id",			CT_CPU_386},
	{"CMPPS",		"xmmreg,r/m128,imm8",		"0F C2 /r ib",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"CMPEQPS",		"xmmreg,r/m128",			"0F C2 /r 00",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"CMPLEPS",		"xmmreg,r/m128",			"0F C2 /r 02",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"CMPLTPS",		"xmmreg,r/m128",			"0F C2 /r 01",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"CMPNEQPS",	"xmmreg,r/m128",			"0F C2 /r 04",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"CMPNLEPS",	"xmmreg,r/m128",			"0F C2 /r 06",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"CMPNLTPS",	"xmmreg,r/m128",			"0F C2 /r 05",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"CMPORDPS",	"xmmreg,r/m128",			"0F C2 /r 07",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"CMPUNORDPS",	"xmmreg,r/m128",			"0F C2 /r 03",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"CMPSB",		"",							"A6",				CT_CPU_8086},
	{"CMPSW",		"",							"po A7",			CT_CPU_8086},
	{"CMPSD",		"",							"po A7",			CT_CPU_386},
	{"CMPSS",		"xmmreg,xmmreg/mem32,imm8",	"p3 0F C2 /r ib",	CT_CPU_KATMAI | CT_CPU_SSE},
	{"CMPEQSS",		"xmmreg,xmmreg/mem32",		"p3 0F C2 /r 00",	CT_CPU_KATMAI | CT_CPU_SSE},
	{"CMPLESS",		"xmmreg,xmmreg/mem32",		"p3 0F C2 /r 02",	CT_CPU_KATMAI | CT_CPU_SSE},
	{"CMPLTSS",		"xmmreg,xmmreg/mem32",		"p3 0F C2 /r 01",	CT_CPU_KATMAI | CT_CPU_SSE},
	{"CMPNEQSS",	"xmmreg,xmmreg/mem32",		"p3 0F C2 /r 04",	CT_CPU_KATMAI | CT_CPU_SSE},
	{"CMPNLESS",	"xmmreg,xmmreg/mem32",		"p3 0F C2 /r 06",	CT_CPU_KATMAI | CT_CPU_SSE},
	{"CMPNLTSS",	"xmmreg,xmmreg/mem32",		"p3 0F C2 /r 05",	CT_CPU_KATMAI | CT_CPU_SSE},
	{"CMPORDSS",	"xmmreg,xmmreg/mem32",		"p3 0F C2 /r 07",	CT_CPU_KATMAI | CT_CPU_SSE},
	{"CMPUNORDSS",	"xmmreg,xmmreg/mem32",		"p3 0F C2 /r 03",	CT_CPU_KATMAI | CT_CPU_SSE},
	{"CMPXCHG",		"r/m8,reg8",				"0F B0 /r",			CT_CPU_PENT},
	{"CMPXCHG",		"r/m16,reg16",				"po 0F B1 /r",		CT_CPU_PENT},
	{"CMPXCHG",		"r/m32,reg32",				"po 0F B1 /r",		CT_CPU_PENT},
//	{"CMPXCHG486",	"r/m8,reg8",				"0F A6 /r",			CT_CPU_486 | CT_CPU_UNDOC},
//	{"CMPXCHG486",	"r/m16,reg16",				"po 0F A7 /r",		CT_CPU_486 | CT_CPU_UNDOC},
//	{"CMPXCHG486",	"r/m32,reg32",				"po 0F A7 /r",		CT_CPU_486 | CT_CPU_UNDOC},
	{"CMPXCHG8B",	"mem",						"0F C7 /1",			CT_CPU_PENT},
	{"COMISS",		"xmmreg,xmmreg/mem32",		"0F 2F /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"CPUID",		"",							"0F A2",			CT_CPU_PENT},
	{"CVTPI2PS",	"xmmreg,r/m64",				"0F 2A /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"CVTPS2PI",	"mmreg,xmmreg/mem64",		"0F 2D /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"CVTTPS2PI",	"mmreg,xmmreg/mem64",		"0F 2C /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"CVTSI2SS",	"xmmreg,r/m32",				"p3 0F 2A /r",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"CVTSS2SI",	"reg32,xmmreg/mem32",		"p3 0F 2D /r",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"CVTTSS2SI",	"reg32,xmmreg/mem32",		"p3 0F 2C /r",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"DAA",			"",							"27",				CT_CPU_8086},
	{"DAS",			"",							"2F",				CT_CPU_8086},
	{"DEC",			"reg16",					"po 48 +r",			CT_CPU_8086},
	{"DEC",			"reg32",					"po 48 +r",			CT_CPU_386},
	{"DEC",			"BYTE r/m8",				"FE /1",			CT_CPU_8086},
	{"DEC",			"WORD r/m16",				"po FF /1",			CT_CPU_8086},
	{"DEC",			"DWORD r/m32",				"po FF /1",			CT_CPU_386},
	{"DIV",			"BYTE r/m8",				"F6 /6",			CT_CPU_8086},
	{"DIV",			"WORD r/m16",				"po F7 /6",			CT_CPU_8086},
	{"DIV",			"DWORD r/m32",				"po F7 /6",			CT_CPU_386},
	{"DIVPS",		"xmmreg,r/m128",			"0F 5E /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"DIVSS",		"xmmreg,xmmreg/mem32",		"p3 0F 5E /r",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"EMMS",		"",							"0F 77",			CT_CPU_PENT | CT_CPU_MMX},
//	{"ENTER",		"imm,imm",					"C8 iw ib",			CT_CPU_186},
	{"F2XM1",		"",							"D9 F0",			CT_CPU_8086 | CT_CPU_FPU},
	{"FABS",		"",							"D9 E1",			CT_CPU_8086 | CT_CPU_FPU},
	{"FADD",		"DWORD mem32",				"D8 /0",			CT_CPU_8086 | CT_CPU_FPU},
	{"FADD",		"QWORD mem64",				"DC /0",			CT_CPU_8086 | CT_CPU_FPU},
	{"FADD",		"fpureg",					"D8 C0 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FADD",		"ST0,fpureg",				"D8 C0 +r",			CT_CPU_8086 | CT_CPU_FPU},
//	{"FADD",		"TO fpureg",				"DC C0 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FADD",		"fpureg,ST0",				"DC C0 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FADDP",		"fpureg",					"DE C0 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FADDP",		"fpureg,ST0",				"DE C0 +r",			CT_CPU_8086 | CT_CPU_FPU},
//	{"FBLD",		"mem80",					"DF /4",			CT_CPU_8086 | CT_CPU_FPU},
//	{"FBSTP",		"mem80",					"DF /6",			CT_CPU_8086 | CT_CPU_FPU},
	{"FCHS",		"",							"D9 E0",			CT_CPU_8086 | CT_CPU_FPU},
	{"FCLEX",		"",							"9B DB E2",			CT_CPU_8086 | CT_CPU_FPU},
	{"FNCLEX",		"",							"DB E2",			CT_CPU_8086 | CT_CPU_FPU},
	{"FCMOVB",		"fpureg",					"DA C0 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCMOVB",		"ST0,fpureg",				"DA C0 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCMOVBE",		"fpureg",					"DA D0 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCMOVBE",		"ST0,fpureg",				"DA D0 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCMOVE",		"fpureg",					"DA C8 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCMOVE",		"ST0,fpureg",				"DA C8 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCMOVNB",		"fpureg",					"DB C0 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCMOVNB",		"ST0,fpureg",				"DB C0 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCMOVNBE",	"fpureg",					"DB D0 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCMOVNBE",	"ST0,fpureg",				"DB D0 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCMOVNE",		"fpureg",					"DB C8 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCMOVNE",		"ST0,fpureg",				"DB C8 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCMOVNU",		"fpureg",					"DB D8 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCMOVNU",		"ST0,fpureg",				"DB D8 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCMOVU",		"fpureg",					"DA D8 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCMOVU",		"ST0,fpureg",				"DA D8 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCOM",		"DWORD mem32",				"D8 /2",			CT_CPU_8086 | CT_CPU_FPU},
	{"FCOM",		"QWORD mem64",				"DC /2",			CT_CPU_8086 | CT_CPU_FPU},
	{"FCOM",		"fpureg",					"D8 D0 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FCOM",		"ST0,fpureg",				"D8 D0 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FCOMP",		"DWORD mem32",				"D8 /3",			CT_CPU_8086 | CT_CPU_FPU},
	{"FCOMP",		"QWORD mem64",				"DC /3",			CT_CPU_8086 | CT_CPU_FPU},
	{"FCOMP",		"fpureg",					"D8 D8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FCOMP",		"ST0,fpureg",				"D8 D8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FCOMPP",		"",							"DE D9",			CT_CPU_8086 | CT_CPU_FPU},
	{"FCOMI",		"fpureg",					"DB F0 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCOMI",		"ST0,fpureg",				"DB F0 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCOMIP",		"fpureg",					"DF F0 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCOMIP",		"ST0,fpureg",				"DF F0 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FCOS",		"",							"D9 FF",			CT_CPU_386 | CT_CPU_FPU},
	{"FDECSTP",		"",							"D9 F6",			CT_CPU_8086 | CT_CPU_FPU},
	{"FDISI",		"",							"9B DB E1",			CT_CPU_8086 | CT_CPU_FPU},
	{"FNDISI",		"",							"DB E1",			CT_CPU_8086 | CT_CPU_FPU},
	{"FENI",		"",							"9B DB E0",			CT_CPU_8086 | CT_CPU_FPU},
	{"FNENI",		"",							"DB E0",			CT_CPU_8086 | CT_CPU_FPU},
	{"FDIV",		"DWORD mem32",				"D8 /6",			CT_CPU_8086 | CT_CPU_FPU},
	{"FDIV",		"QWORD mem64",				"DC /6",			CT_CPU_8086 | CT_CPU_FPU},
	{"FDIV",		"fpureg",					"D8 F0 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FDIV",		"ST0,fpureg",				"D8 F0 +r",			CT_CPU_8086 | CT_CPU_FPU},
//	{"FDIV",		"TO fpureg",				"DC F8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FDIV",		"fpureg,ST0",				"DC F8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FDIVR",		"DWORD mem32",				"D8 /7",			CT_CPU_8086 | CT_CPU_FPU},
	{"FDIVR",		"QWORD mem64",				"DC /7",			CT_CPU_8086 | CT_CPU_FPU},
	{"FDIVR",		"fpureg",					"D8 F8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FDIVR",		"ST0,fpureg",				"D8 F8 +r",			CT_CPU_8086 | CT_CPU_FPU},
//	{"FDIVR",		"TO fpureg",				"DC F0 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FDIVR",		"fpureg,ST0",				"DC F0 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FDIVP",		"fpureg",					"DE F8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FDIVP",		"fpureg,ST0",				"DE F8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FDIVRP",		"fpureg",					"DE F0 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FDIVRP",		"fpureg,ST0",				"DE F0 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FEMMS",		"",							"0F 0E",			CT_CPU_3DNOW},
	{"FFREE",		"fpureg",					"DD C0 +r",			CT_CPU_8086 | CT_CPU_FPU},
//	{"FFREEP",		"fpureg",					"DF C0 +r",			CT_CPU_P6 | CT_CPU_FPU | CT_CPU_UNDOC},
	{"FIADD",		"WORD mem16",				"DE /0",			CT_CPU_8086 | CT_CPU_FPU},
	{"FIADD",		"DWORD mem32",				"DA /0",			CT_CPU_8086 | CT_CPU_FPU},
	{"FICOM",		"WORD mem16",				"DE /2",			CT_CPU_8086 | CT_CPU_FPU},
	{"FICOM",		"DWORD mem32",				"DA /2",			CT_CPU_8086 | CT_CPU_FPU},
	{"FICOMP",		"WORD mem16",				"DE /3",			CT_CPU_8086 | CT_CPU_FPU},
	{"FICOMP",		"DWORD mem32",				"DA /3",			CT_CPU_8086 | CT_CPU_FPU},
	{"FIDIV",		"WORD mem16",				"DE /6",			CT_CPU_8086 | CT_CPU_FPU},
	{"FIDIV",		"DWORD mem32",				"DA /6",			CT_CPU_8086 | CT_CPU_FPU},
	{"FIDIVR",		"WORD mem16",				"DE /7",			CT_CPU_8086 | CT_CPU_FPU},
	{"FIDIVR",		"DWORD mem32",				"DA /7",			CT_CPU_8086 | CT_CPU_FPU},
	{"FILD",		"WORD mem16",				"DF /0",			CT_CPU_8086 | CT_CPU_FPU},
	{"FILD",		"DWORD mem32",				"DB /0",			CT_CPU_8086 | CT_CPU_FPU},
	{"FILD",		"QWORD mem64",				"DF /5",			CT_CPU_8086 | CT_CPU_FPU},
	{"FIST",		"WORD mem16",				"DF /2",			CT_CPU_8086 | CT_CPU_FPU},
	{"FIST",		"DWORD mem32",				"DB /2",			CT_CPU_8086 | CT_CPU_FPU},
	{"FISTP",		"WORD mem16",				"DF /3",			CT_CPU_8086 | CT_CPU_FPU},
	{"FISTP",		"DWORD mem32",				"DB /3",			CT_CPU_8086 | CT_CPU_FPU},
	{"FISTP",		"QWORD mem64",				"DF /0",			CT_CPU_8086 | CT_CPU_FPU},
	{"FIMUL",		"WORD mem16",				"DE /1",			CT_CPU_8086 | CT_CPU_FPU},
	{"FIMUL",		"DWORD mem32",				"DA /1",			CT_CPU_8086 | CT_CPU_FPU},
	{"FINCSTP",		"",							"D9 F7",			CT_CPU_8086 | CT_CPU_FPU},
	{"FINIT",		"",							"9B DB E3",			CT_CPU_8086 | CT_CPU_FPU},
	{"FNINIT",		"",							"DB E3",			CT_CPU_8086 | CT_CPU_FPU},
	{"FISUB",		"WORD mem16",				"DE /4",			CT_CPU_8086 | CT_CPU_FPU},
	{"FISUB",		"DWORD mem32",				"DA /4",			CT_CPU_8086 | CT_CPU_FPU},
	{"FISUBR",		"WORD mem16",				"DE /5",			CT_CPU_8086 | CT_CPU_FPU},
	{"FISUBR",		"DWORD mem32",				"DA /5",			CT_CPU_8086 | CT_CPU_FPU},
	{"FLD",			"DWORD mem32",				"D9 /0",			CT_CPU_8086 | CT_CPU_FPU},
	{"FLD",			"QWORD mem64",				"DD /0",			CT_CPU_8086 | CT_CPU_FPU},
//	{"FLD",			"mem80",					"DB /5",			CT_CPU_8086 | CT_CPU_FPU},
	{"FLD",			"fpureg",					"D9 C0 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FLD1",		"",							"D9 E8",			CT_CPU_8086 | CT_CPU_FPU},
	{"FLDL2E",		"",							"D9 EA",			CT_CPU_8086 | CT_CPU_FPU},
	{"FLDL2T",		"",							"D9 E9",			CT_CPU_8086 | CT_CPU_FPU},
	{"FLDLG2",		"",							"D9 EC",			CT_CPU_8086 | CT_CPU_FPU},
	{"FLDLN2",		"",							"D9 ED",			CT_CPU_8086 | CT_CPU_FPU},
	{"FLDPI",		"",							"D9 EB",			CT_CPU_8086 | CT_CPU_FPU},
	{"FLDZ",		"",							"D9 EE",			CT_CPU_8086 | CT_CPU_FPU},
	{"FLDCW",		"mem16",					"D9 /5",			CT_CPU_8086 | CT_CPU_FPU},
	{"FLDENV",		"mem",						"D9 /4",			CT_CPU_8086 | CT_CPU_FPU},
	{"FMUL",		"DWORD mem32",				"D8 /1",			CT_CPU_8086 | CT_CPU_FPU},
	{"FMUL",		"QWORD mem64",				"DC /1",			CT_CPU_8086 | CT_CPU_FPU},
	{"FMUL",		"fpureg",					"D8 C8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FMUL",		"ST0,fpureg",				"D8 C8 +r",			CT_CPU_8086 | CT_CPU_FPU},
//	{"FMUL",		"TO fpureg",				"DC C8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FMUL",		"fpureg,ST0",				"DC C8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FMULP",		"fpureg",					"DE C8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FMULP",		"fpureg,ST0",				"DE C8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FNOP",		"",							"D9 D0",			CT_CPU_8086 | CT_CPU_FPU},
	{"FPATAN",		"",							"D9 F3",			CT_CPU_8086 | CT_CPU_FPU},
	{"FPTAN",		"",							"D9 F2",			CT_CPU_8086 | CT_CPU_FPU},
	{"FPREM",		"",							"D9 F8",			CT_CPU_8086 | CT_CPU_FPU},
	{"FPREM1",		"",							"D9 F5",			CT_CPU_386 | CT_CPU_FPU},
	{"FRNDINT",		"",							"D9 FC",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSAVE",		"mem",						"9B DD /6",			CT_CPU_8086 | CT_CPU_FPU},
	{"FNSAVE",		"mem",						"DD /6",			CT_CPU_8086 | CT_CPU_FPU},
	{"FRSTOR",		"mem",						"DD /4",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSCALE",		"",							"D9 FD",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSETPM",		"",							"DB E4",			CT_CPU_286 | CT_CPU_FPU},
	{"FSIN",		"",							"D9 FE",			CT_CPU_386 | CT_CPU_FPU},
	{"FSINCOS",		"",							"D9 FB",			CT_CPU_386 | CT_CPU_FPU},
	{"FSQRT",		"",							"D9 FA",			CT_CPU_8086 | CT_CPU_FPU},
	{"FST",			"DWORD mem32",				"D9 /2",			CT_CPU_8086 | CT_CPU_FPU},
	{"FST",			"QWORD mem64",				"DD /2",			CT_CPU_8086 | CT_CPU_FPU},
	{"FST",			"fpureg",					"DD D0 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSTP",		"DWORD mem32",				"D9 /3",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSTP",		"QWORD mem64",				"DD /3",			CT_CPU_8086 | CT_CPU_FPU},
//	{"FSTP",		"mem80",					"DB /0",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSTP",		"fpureg",					"DD D8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSTCW",		"mem16",					"9B D9 /0",			CT_CPU_8086 | CT_CPU_FPU},
	{"FNSTCW",		"mem16",					"D9 /0",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSTENV",		"mem",						"9B D9 /6",			CT_CPU_8086 | CT_CPU_FPU},
	{"FNSTENV",		"mem",						"D9 /6",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSTSW",		"mem16",					"9B DD /0",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSTSW",		"AX",						"9B DF E0",			CT_CPU_286 | CT_CPU_FPU},
	{"FNSTSW",		"mem16",					"DD /0",			CT_CPU_8086 | CT_CPU_FPU},
	{"FNSTSW",		"AX",						"DF E0",			CT_CPU_286 | CT_CPU_FPU},
	{"FSUB",		"DWORD mem32",				"D8 /4",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSUB",		"QWORD mem64",				"DC /4",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSUB",		"fpureg",					"D8 E0 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSUB",		"ST0,fpureg",				"D8 E0 +r",			CT_CPU_8086 | CT_CPU_FPU},
//	{"FSUB",		"TO fpureg",				"DC E8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSUB",		"fpureg,ST0",				"DC E8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSUBR",		"DWORD mem32",				"D8 /5",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSUBR",		"QWORD mem64",				"DC /5",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSUBR",		"fpureg",					"D8 E8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSUBR",		"ST0,fpureg",				"D8 E8 +r",			CT_CPU_8086 | CT_CPU_FPU},
//	{"FSUBR",		"TO fpureg",				"DC E0 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSUBR",		"fpureg,ST0",				"DC E0 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSUBP",		"fpureg",					"DE E8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSUBP",		"fpureg,ST0",				"DE E8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSUBRP",		"fpureg",					"DE E0 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FSUBRP",		"fpureg,ST0",				"DE E0 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FTST",		"",							"D9 E4",			CT_CPU_8086 | CT_CPU_FPU},
	{"FUCOM",		"fpureg",					"DD E0 +r",			CT_CPU_386 | CT_CPU_FPU},
	{"FUCOM",		"ST0,fpureg",				"DD E0 +r",			CT_CPU_386 | CT_CPU_FPU},
	{"FUCOMP",		"fpureg",					"DD E8 +r",			CT_CPU_386 | CT_CPU_FPU},
	{"FUCOMP",		"ST0,fpureg",				"DD E8 +r",			CT_CPU_386 | CT_CPU_FPU},
	{"FUCOMPP",		"",							"DA E9",			CT_CPU_386 | CT_CPU_FPU},
	{"FUCOMI",		"fpureg",					"DB E8 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FUCOMI",		"ST0,fpureg",				"DB E8 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FUCOMIP",		"fpureg",					"DF E8 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FUCOMIP",		"ST0,fpureg",				"DF E8 +r",			CT_CPU_P6 | CT_CPU_FPU},
	{"FWAIT",		"",							"9B",				CT_CPU_8086},
	{"FXAM",		"",							"D9 E5",			CT_CPU_8086 | CT_CPU_FPU},
	{"FXCH",		"",							"D9 C9",			CT_CPU_8086 | CT_CPU_FPU},
	{"FXCH",		"fpureg",					"D9 C8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FXCH",		"fpureg,ST0",				"D9 C8 +r",			CT_CPU_8086 | CT_CPU_FPU},
	{"FXCH",		"ST0,fpureg",				"D9 C8 +r",			CT_CPU_8086 | CT_CPU_FPU},
//	{"FXRSTOR",		"m512byte",					"0F AE /1",			CT_CPU_P6 | CT_CPU_SSE | CT_CPU_FPU},
//	{"FXSAVE",		"m512byte",					"0F AE /0",			CT_CPU_P6 | CT_CPU_SSE | CT_CPU_FPU},
	{"FXTRACT",		"",							"D9 F4",			CT_CPU_8086 | CT_CPU_FPU},
	{"FYL2X",		"",							"D9 F1",			CT_CPU_8086 | CT_CPU_FPU},
	{"FYL2XP1",		"",							"D9 F9",			CT_CPU_8086 | CT_CPU_FPU},
	{"HLT",			"",							"F4",				CT_CPU_8086},
//	{"IBTS",		"r/m16,reg16",				"po 0F A7 /r",		CT_CPU_386 | CT_CPU_UNDOC},
//	{"IBTS",		"r/m32,reg32",				"po 0F A7 /r",		CT_CPU_386 | CT_CPU_UNDOC},
	{"IDIV",		"BYTE r/m8",				"F6 /7",			CT_CPU_8086},
	{"IDIV",		"WORD r/m16",				"po F7 /7",			CT_CPU_8086},
	{"IDIV",		"DWORD r/m32",				"po F7 /7",			CT_CPU_386},
	{"IMUL",		"BYTE r/m8",				"F6 /5",			CT_CPU_8086},
	{"IMUL",		"WORD r/m16",				"po F7 /5",			CT_CPU_8086},
	{"IMUL",		"DWORD r/m32",				"po F7 /5",			CT_CPU_386},
	{"IMUL",		"reg16,r/m16",				"po 0F AF /r",		CT_CPU_386},
	{"IMUL",		"reg32,r/m32",				"po 0F AF /r",		CT_CPU_386},
	{"IMUL",		"reg16,imm8",				"po 6B /r ib",		CT_CPU_286},
	{"IMUL",		"reg16,imm16",				"po 69 /r iw",		CT_CPU_286},
	{"IMUL",		"reg32,imm8",				"po 6B /r ib",		CT_CPU_386},
	{"IMUL",		"reg32,imm32",				"po 69 /r id",		CT_CPU_386},
	{"IMUL",		"reg16,r/m16,imm8",			"po 6B /r ib",		CT_CPU_286},
	{"IMUL",		"reg16,r/m16,imm16",		"po 69 /r iw",		CT_CPU_286},
	{"IMUL",		"reg32,r/m32,imm8",			"po 6B /r ib",		CT_CPU_386},
	{"IMUL",		"reg32,r/m32,imm32",		"po 69 /r id",		CT_CPU_386},
	{"IN",			"AL,imm8",					"E4 ib",			CT_CPU_8086},
	{"IN",			"AX,imm8",					"po E5 ib",			CT_CPU_8086},
	{"IN",			"EAX,imm8",					"po E5 ib",			CT_CPU_386},
	{"IN",			"AL,DX",					"EC",				CT_CPU_8086},
	{"IN",			"AX,DX",					"po ED",			CT_CPU_8086},
	{"IN",			"EAX,DX",					"po ED",			CT_CPU_386},
	{"INC",			"reg16",					"po 40 +r",			CT_CPU_8086},
	{"INC",			"reg32",					"po 40 +r",			CT_CPU_386},
	{"INC",			"BYTE r/m8",				"FE /0",			CT_CPU_8086},
	{"INC",			"WORD r/m16",				"po FF /0",			CT_CPU_8086},
	{"INC",			"DWORD r/m32",				"po FF /0",			CT_CPU_386},
	{"INSB",		"",							"6C",				CT_CPU_186},
	{"INSW",		"",							"po 6D",			CT_CPU_186},
	{"INSD",		"",							"po 6D",			CT_CPU_386},
	{"INT",			"imm8",						"CD ib",			CT_CPU_8086},
	{"INT1",		"",							"F1",				CT_CPU_P6},
	{"ICEBP",		"",							"F1",				CT_CPU_P6},
	{"INT01",		"",							"F1",				CT_CPU_P6},
	{"INT3",		"",							"CC",				CT_CPU_8086},
	{"INT03",		"",							"CC",				CT_CPU_8086},
	{"INTO",		"",							"CE",				CT_CPU_8086},
	{"INVD",		"",							"0F 08",			CT_CPU_486},
	{"INVLPG",		"mem",						"0F 01 /0",			CT_CPU_486},
	{"IRET",		"",							"CF",				CT_CPU_8086},
	{"IRETW",		"",							"po CF",			CT_CPU_8086},
	{"IRETD",		"",							"po CF",			CT_CPU_386},
	{"JCXZ",		"imm",						"po E3 -b",			CT_CPU_8086},
	{"JECXZ",		"imm",						"po E3 -b",			CT_CPU_386},
	{"JMP",			"imm",						"E9 -i",			CT_CPU_8086},
	{"JMP",			"SHORT imm",				"EB -b",			CT_CPU_8086},
//	{"JMP",			"imm:imm16",				"po EA iw iw",		CT_CPU_8086},
//	{"JMP",			"imm:imm32",				"po EA id iw",		CT_CPU_386},
	{"JMP",			"mem",						"po FF /5",			CT_CPU_8086},
//	{"JMP",			"FAR mem",					"po FF /5",			CT_CPU_386},
	{"JMP",			"WORD r/m16",				"po FF /4",			CT_CPU_8086},
	{"JMP",			"DWORD r/m32",				"po FF /4",			CT_CPU_386},
	{"JO",			"imm",						"70 -b",			CT_CPU_8086},
	{"JNO",			"imm",						"71 -b",			CT_CPU_8086},
	{"JB",			"imm",						"72 -b",			CT_CPU_8086},
	{"JC",			"imm",						"72 -b",			CT_CPU_8086},
	{"JNEA",		"imm",						"72 -b",			CT_CPU_8086},
	{"JAE",			"imm",						"73 -b",			CT_CPU_8086},
	{"JNB",			"imm",						"73 -b",			CT_CPU_8086},
	{"JNC",			"imm",						"73 -b",			CT_CPU_8086},
	{"JE",			"imm",						"74 -b",			CT_CPU_8086},
	{"JZ",			"imm",						"74 -b",			CT_CPU_8086},
	{"JNE",			"imm",						"75 -b",			CT_CPU_8086},
	{"JNZ",			"imm",						"75 -b",			CT_CPU_8086},
	{"JBE",			"imm",						"76 -b",			CT_CPU_8086},
	{"JNA",			"imm",						"76 -b",			CT_CPU_8086},
	{"JA",			"imm",						"77 -b",			CT_CPU_8086},
	{"JNBE",		"imm",						"77 -b",			CT_CPU_8086},
	{"JS",			"imm",						"78 -b",			CT_CPU_8086},
//	{"JNS",			"imm",						"79 -b",			CT_CPU_8086},
	{"JP",			"imm",						"7A -b",			CT_CPU_8086},
	{"JPE",			"imm",						"7A -b",			CT_CPU_8086},
	{"JNP",			"imm",						"7B -b",			CT_CPU_8086},
	{"JPO",			"imm",						"7B -b",			CT_CPU_8086},
	{"JL",			"imm",						"7C -b",			CT_CPU_8086},
	{"JNGE",		"imm",						"7C -b",			CT_CPU_8086},
	{"JGE",			"imm",						"7D -b",			CT_CPU_8086},
	{"JNL",			"imm",						"7D -b",			CT_CPU_8086},
	{"JLE",			"imm",						"7E -b",			CT_CPU_8086},
	{"JNG",			"imm",						"7E -b",			CT_CPU_8086},
	{"JG",			"imm",						"7F -b",			CT_CPU_8086},
	{"JNLE",		"imm",						"7F -b",			CT_CPU_8086},
	{"JO",			"NEAR imm",					"0F 80 -i",			CT_CPU_386},
	{"JNO",			"NEAR imm",					"0F 81 -i",			CT_CPU_386},
	{"JB",			"NEAR imm",					"0F 82 -i",			CT_CPU_386},
	{"JC",			"NEAR imm",					"0F 82 -i",			CT_CPU_386},
	{"JNEA",		"NEAR imm",					"0F 82 -i",			CT_CPU_386},
	{"JAE",			"NEAR imm",					"0F 83 -i",			CT_CPU_386},
	{"JNB",			"NEAR imm",					"0F 83 -i",			CT_CPU_386},
	{"JNC",			"NEAR imm",					"0F 83 -i",			CT_CPU_386},
	{"JE",			"NEAR imm",					"0F 84 -i",			CT_CPU_386},
	{"JZ",			"NEAR imm",					"0F 84 -i",			CT_CPU_386},
	{"JNE",			"NEAR imm",					"0F 85 -i",			CT_CPU_386},
	{"JNZ",			"NEAR imm",					"0F 85 -i",			CT_CPU_386},
	{"JBE",			"NEAR imm",					"0F 86 -i",			CT_CPU_386},
	{"JNA",			"NEAR imm",					"0F 86 -i",			CT_CPU_386},
	{"JA",			"NEAR imm",					"0F 87 -i",			CT_CPU_386},
	{"JNBE",		"NEAR imm",					"0F 87 -i",			CT_CPU_386},
	{"JS",			"NEAR imm",					"0F 88 -i",			CT_CPU_386},
	{"JNS",			"NEAR imm",					"0F 89 -i",			CT_CPU_386},
	{"JP",			"NEAR imm",					"0F 8A -i",			CT_CPU_386},
	{"JPE",			"NEAR imm",					"0F 8A -i",			CT_CPU_386},
	{"JNP",			"NEAR imm",					"0F 8B -i",			CT_CPU_386},
	{"JPO",			"NEAR imm",					"0F 8B -i",			CT_CPU_386},
	{"JL",			"NEAR imm",					"0F 8C -i",			CT_CPU_386},
	{"JNGE",		"NEAR imm",					"0F 8C -i",			CT_CPU_386},
	{"JGE",			"NEAR imm",					"0F 8D -i",			CT_CPU_386},
	{"JNL",			"NEAR imm",					"0F 8D -i",			CT_CPU_386},
	{"JLE",			"NEAR imm",					"0F 8E -i",			CT_CPU_386},
	{"JNG",			"NEAR imm",					"0F 8E -i",			CT_CPU_386},
	{"JG",			"NEAR imm",					"0F 8F -i",			CT_CPU_386},
	{"JNLE",		"NEAR imm",					"0F 8F -i",			CT_CPU_386},
	{"LAHF",		"",							"9F",				CT_CPU_8086},
//	{"LAR",			"reg16,r/m16",				"po 0F 02 /r",		CT_CPU_286 | CT_CPU_PRIV},
//	{"LAR",			"reg32,r/m32",				"po 0F 02 /r",		CT_CPU_286 | CT_CPU_PRIV},
	{"LDS",			"reg16,mem",				"po C5 /r",			CT_CPU_8086},
	{"LDS",			"reg32,mem",				"po C5 /r",			CT_CPU_8086},
	{"LES",			"reg16,mem",				"po C4 /r",			CT_CPU_8086},
	{"LES",			"reg32,mem",				"po C4 /r",			CT_CPU_8086},
	{"LFS",			"reg16,mem",				"po 0F B4 /r",		CT_CPU_386},
	{"LFS",			"reg32,mem",				"po 0F B4 /r",		CT_CPU_386},
	{"LGS",			"reg16,mem",				"po 0F B5 /r",		CT_CPU_386},
	{"LGS",			"reg32,mem",				"po 0F B5 /r",		CT_CPU_386},
	{"LSS",			"reg16,mem",				"po 0F B2 /r",		CT_CPU_386},
	{"LSS",			"reg32,mem",				"po 0F B2 /r",		CT_CPU_386},
	{"LDMXCSR",		"mem32",					"0F AE /2",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"LEA",			"reg16,mem",				"po 8D /r",			CT_CPU_8086},
	{"LEA",			"reg32,mem",				"po 8D /r",			CT_CPU_386},
	{"LEAVE",		"",							"C9",				CT_CPU_186},
//	{"LGDT",		"mem",						"0F 01 /2",			CT_CPU_286 | CT_CPU_PRIV},
//	{"LIDT",		"mem",						"0F 01 /3",			CT_CPU_286 | CT_CPU_PRIV},
//	{"LLDT",		"r/m16",					"0F 00 /2",			CT_CPU_286 | CT_CPU_PRIV},
//	{"LMSW",		"r/m16",					"0F 01 /6",			CT_CPU_286 | CT_CPU_PRIV},
//	{"LOADALL",		"",							"0F 07",			CT_CPU_386 | CT_CPU_UNDOC},
//	{"LOADALL286",	"",							"0F 05",			CT_CPU_286 | CT_CPU_UNDOC},
	{"LODSB",		"",							"AC",				CT_CPU_8086},
	{"LODSW",		"",							"po AD",			CT_CPU_8086},
	{"LODSD",		"",							"po AD",			CT_CPU_386},
	{"LOOP",		"imm",						"E2 -b",			CT_CPU_8086},
	{"LOOP",		"imm,CX",					"pa E2 -b",			CT_CPU_8086},
	{"LOOP",		"imm,ECX",					"pa E2 -b",			CT_CPU_386},
	{"LOOPE",		"imm",						"E1 -b",			CT_CPU_8086},
	{"LOOPE",		"imm,CX",					"pa E1 -b",			CT_CPU_8086},
	{"LOOPE",		"imm,ECX",					"pa E1 -b",			CT_CPU_386},
	{"LOOPZ",		"imm",						"E1 -b",			CT_CPU_8086},
	{"LOOPZ",		"imm,CX",					"pa E1 -b",			CT_CPU_8086},
	{"LOOPZ",		"imm,ECX",					"pa E1 -b",			CT_CPU_386},
	{"LOOPNE",		"imm",						"E0 -b",			CT_CPU_8086},
	{"LOOPNE",		"imm,CX",					"pa E0 -b",			CT_CPU_8086},
	{"LOOPNE",		"imm,ECX",					"pa E0 -b",			CT_CPU_386},
	{"LOOPNZ",		"imm",						"E0 -b",			CT_CPU_8086},
	{"LOOPNZ",		"imm,CX",					"pa E0 -b",			CT_CPU_8086},
	{"LOOPNZ",		"imm,ECX",					"pa E0 -b",			CT_CPU_386},
//	{"LSL",			"reg16,r/m16",				"po 0F 03 /r",		CT_CPU_286 | CT_CPU_PRIV},
//	{"LSL",			"reg32,r/m32",				"po 0F 03 /r",		CT_CPU_286 | CT_CPU_PRIV},
//	{"LTR",			"r/m16",					"0F 00 /3",			CT_CPU_286 | CT_CPU_PRIV},
	{"MASKMOVQ",	"mmreg,mmreg",				"0F F7 /r",			CT_CPU_KATMAI},
//	{"MAXPS",		"xmmreg,r/m128",			"0F 5F /r",			CT_CPU_KATMAI | CT_CPU_SSE},
//	{"MAXSS",		"xmmreg,r/m128",			"p3 0F 5F /r",		CT_CPU_KATMAI | CT_CPU_SSE},
//	{"MINPS",		"xmmreg,r/m128",			"0F 5D /r",			CT_CPU_KATMAI | CT_CPU_SSE},
//	{"MINSS",		"xmmreg,r/m128",			"p3 0F 5D /r",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"MOV",			"r/m8,reg8",				"88 /r",			CT_CPU_8086},
	{"MOV",			"r/m16,reg16",				"po 89 /r",			CT_CPU_8086},
	{"MOV",			"r/m32,reg32",				"po 89 /r",			CT_CPU_386},
	{"MOV",			"reg8,r/m8",				"8A /r",			CT_CPU_8086},
	{"MOV",			"reg16,r/m16",				"po 8B /r",			CT_CPU_8086},
	{"MOV",			"reg32,r/m32",				"po 8B /r",			CT_CPU_386},
	{"MOV",			"reg8,imm8",				"B0 +r ib",			CT_CPU_8086},
	{"MOV",			"reg16,imm16",				"po B8 +r iw",		CT_CPU_8086},
	{"MOV",			"reg32,imm32",				"po B8 +r id",		CT_CPU_386},
	{"MOV",			"r/m8,imm8",				"C6 /0 ib",			CT_CPU_8086},
	{"MOV",			"r/m16,imm16",				"po C7 /0 iw",		CT_CPU_8086},
	{"MOV",			"r/m32,imm32",				"po C7 /0 id",		CT_CPU_386},
//	{"MOV",			"AL,memoffs8",				"A0 id",			CT_CPU_8086},
//	{"MOV",			"AX,memoffs16",				"po A1 id",			CT_CPU_8086},
//	{"MOV",			"EAX,memoffs32",			"po A1 id",			CT_CPU_386},
//	{"MOV",			"memoffs8,AL",				"A2 id",			CT_CPU_8086},
//	{"MOV",			"memoffs16,AX",				"po A3 id",			CT_CPU_8086},
//	{"MOV",			"memoffs32,EAX",			"po A3 id",			CT_CPU_386},
//	{"MOV",			"r/m16,segreg",				"po 8C /r",			CT_CPU_8086},
//	{"MOV",			"r/m32,segreg",				"po 8C /r",			CT_CPU_386},
//	{"MOV",			"segreg,r/m16",				"po 8E /r",			CT_CPU_8086},
//	{"MOV",			"segreg,r/m32",				"po 8E /r",			CT_CPU_386},
//	{"MOV",			"reg32,CR0/2/3/4",			"0F 20 /r",			CT_CPU_386},
//	{"MOV",			"reg32,DR0/1/2/3/6/7",		"0F 21 /r",			CT_CPU_386},
//	{"MOV",			"reg32,TR3/4/5/6/7",		"0F 24 /r",			CT_CPU_386},
//	{"MOV",			"CR0/2/3/4,reg32",			"0F 22 /r",			CT_CPU_386},
//	{"MOV",			"DR0/1/2/3/6/7,reg32",		"0F 23 /r",			CT_CPU_386},
//	{"MOV",			"TR3/4/5/6/7,reg32",		"0F 26 /r",			CT_CPU_386},
	{"MOVAPS",		"xmmreg,r/m128",			"0F 28 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"MOVAPS",		"r/m128,xmmreg",			"0F 29 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"MOVD",		"mmreg,r/m32",				"0F 6E /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"MOVD",		"r/m32,mmreg",				"0F 7E /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"MOVHLPS",		"xmmreg,xmmreg",			"0F 12 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"MOVHPS",		"xmmreg,mem64",				"0F 16 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"MOVHPS",		"mem64,xmmreg",				"0F 17 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"MOVHPS",		"xmmreg,xmmreg",			"0F 16 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"MOVLHPS",		"xmmreg,xmmreg",			"0F 16 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"MOVLPS",		"xmmreg,mem64",				"0F 12 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"MOVLPS",		"mem64,xmmreg",				"0F 13 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"MOVLPS",		"xmmreg,xmmreg",			"0F 12 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"MOVMSKPS",	"reg32,xmmreg",				"0F 50 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"MOVNTPS",		"mem128,xmmreg",			"0F 2B /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"MOVNTQ",		"mem64,mmreg",				"0F E7 /r",			CT_CPU_KATMAI},
	{"MOVQ",		"mmreg,r/m64",				"0F 6F /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"MOVQ",		"r/m64,mmreg",				"0F 7F /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"MOVSB",		"",							"A4",				CT_CPU_8086},
	{"MOVSW",		"",							"po A5",			CT_CPU_8086},
	{"MOVSD",		"",							"po A5",			CT_CPU_386},
	{"MOVSS",		"xmmreg,xmmreg/mem32",		"p3 0F 10 /r",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"MOVSS",		"xmmreg/mem32,xmmreg",		"p3 0F 11 /r",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"MOVSX",		"reg16,r/m8",				"po 0F BE /r",		CT_CPU_386},
	{"MOVSX",		"reg32,r/m8",				"po 0F BE /r",		CT_CPU_386},
	{"MOVSX",		"reg32,r/m16",				"po 0F BF /r",		CT_CPU_386},
	{"MOVZX",		"reg16,r/m8",				"po 0F B6 /r",		CT_CPU_386},
	{"MOVZX",		"reg32,r/m8",				"po 0F B6 /r",		CT_CPU_386},
	{"MOVZX",		"reg32,r/m16",				"po 0F B7 /r",		CT_CPU_386},
	{"MOVUPS",		"xmmreg,r/m128",			"0F 10 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"MOVUPS",		"r/m128,xmmreg",			"0F 11 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"MUL",			"BYTE r/m8",				"F6 /4",			CT_CPU_8086},
	{"MUL",			"WORD r/m16",				"po F7 /4",			CT_CPU_8086},
	{"MUL",			"DWORD r/m32",				"po F7 /4",			CT_CPU_386},
	{"MULPS",		"xmmreg,r/m128",			"0F 59 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"MULSS",		"xmmreg,xmmreg/mem32",		"p3 0F 59 /r",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"NEG",			"BYTE r/m8",				"F6 /3",			CT_CPU_8086},
	{"NEG",			"WORD r/m16",				"po F7 /3",			CT_CPU_8086},
	{"NEG",			"DWORD r/m32",				"po F7 /3",			CT_CPU_386},
	{"NOT",			"BYTE r/m8",				"F6 /2",			CT_CPU_8086},
	{"NOT",			"WORD r/m16",				"po F7 /2",			CT_CPU_8086},
	{"NOT",			"DWORD r/m32",				"po F7 /2",			CT_CPU_386},
	{"NOP",			"",							"90",				CT_CPU_8086},
	{"OR",			"r/m8,reg8",				"08 /r",			CT_CPU_8086},
	{"OR",			"r/m16,reg16",				"po 09 /r",			CT_CPU_8086},
	{"OR",			"r/m32,reg32",				"po 09 /r",			CT_CPU_386},
	{"OR",			"reg8,r/m8",				"0A /r",			CT_CPU_8086},
	{"OR",			"reg16,r/m16",				"po 0B /r",			CT_CPU_8086},
	{"OR",			"reg32,r/m32",				"po 0B /r",			CT_CPU_386},
	{"OR",			"r/m8,imm8",				"80 /1 ib",			CT_CPU_8086},
	{"OR",			"r/m16,imm16",				"po 81 /1 iw",		CT_CPU_8086},
	{"OR",			"r/m32,imm32",				"po 81 /1 id",		CT_CPU_386},
	{"OR",			"r/m16,imm8",				"po 83 /1 ib",		CT_CPU_8086},
	{"OR",			"r/m32,imm8",				"po 83 /1 ib",		CT_CPU_386},
	{"OR",			"AL,imm8",					"0C ib",			CT_CPU_8086},
	{"OR",			"AX,imm16",					"po 0D iw",			CT_CPU_8086},
	{"OR",			"EAX,imm32",				"po 0D id",			CT_CPU_386},
	{"ORPS",		"xmmreg,r/m128",			"0F 56 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"OUT",			"imm8,AL",					"E6 ib",			CT_CPU_8086},
	{"OUT",			"imm8,AX",					"po E7 ib",			CT_CPU_8086},
	{"OUT",			"imm8,EAX",					"po E7 ib",			CT_CPU_386},
	{"OUT",			"DX,AL",					"EE",				CT_CPU_8086},
	{"OUT",			"DX,AX",					"po EF",			CT_CPU_8086},
	{"OUT",			"DX,EAX",					"po EF",			CT_CPU_386},
	{"OUTSB",		"",							"6E",				CT_CPU_186},
	{"OUTSW",		"",							"po 6F",			CT_CPU_186},
	{"OUTSD",		"",							"po 6F",			CT_CPU_386},
	{"PACKSSDW",	"mmreg,r/m64",				"0F 6B /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PACKSSWB",	"mmreg,r/m64",				"0F 63 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PACKUSWB",	"mmreg,r/m64",				"0F 67 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PADDB",		"mmreg,r/m64",				"0F FC /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PADDW",		"mmreg,r/m64",				"0F FD /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PADDD",		"mmreg,r/m64",				"0F FE /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PADDSB",		"mmreg,r/m64",				"0F EC /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PADDSW",		"mmreg,r/m64",				"0F ED /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PADDUSB",		"mmreg,r/m64",				"0F DC /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PADDUSW",		"mmreg,r/m64",				"0F DD /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PADDSIW",		"mmreg,r/m64",				"0F 51 /r",			CT_CPU_CYRIX | CT_CPU_MMX},
	{"PAND",		"mmreg,r/m64",				"0F DB /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PANDN",		"mmreg,r/m64",				"0F DF /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PAVEB",		"mmreg,r/m64",				"0F 50 /r",			CT_CPU_CYRIX | CT_CPU_MMX},
	{"PAVGB",		"mmreg,r/m64",				"0F E0 /r",			CT_CPU_KATMAI},
	{"PAVGW",		"mmreg,r/m64",				"0F E3 /r",			CT_CPU_KATMAI},
	{"PAVGUSB",		"mmreg,r/m64",				"0F 0F /r BF",		CT_CPU_3DNOW},
	{"PCMPEQB",		"mmreg,r/m64",				"0F 74 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PCMPEQW",		"mmreg,r/m64",				"0F 75 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PCMPEQD",		"mmreg,r/m64",				"0F 76 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PCMPGTB",		"mmreg,r/m64",				"0F 64 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PCMPGTW",		"mmreg,r/m64",				"0F 65 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PCMPGTD",		"mmreg,r/m64",				"0F 66 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PDISTIB",		"mmreg,mem64",				"0F 54 /r",			CT_CPU_CYRIX | CT_CPU_MMX},
	{"PEXTRW",		"reg32,mmreg,imm8",			"0F C5 /r ib",		CT_CPU_KATMAI},
	{"PF2ID",		"mmreg,r/m64",				"0F 0F /r 1D",		CT_CPU_3DNOW},
	{"PF2IW",		"mmreg,r/m64",				"0F 0F /r 1C",		CT_CPU_ATHLON},
	{"PFACC",		"mmreg,r/m64",				"0F 0F /r AE",		CT_CPU_3DNOW},
	{"PFADD",		"mmreg,r/m64",				"0F 0F /r 9E",		CT_CPU_3DNOW},
	{"PFCMPEQ",		"mmreg,r/m64",				"0F 0F /r B0",		CT_CPU_3DNOW},
	{"PFCMPGE",		"mmreg,r/m64",				"0F 0F /r 90",		CT_CPU_3DNOW},
	{"PFCMPGT",		"mmreg,r/m64",				"0F 0F /r A0",		CT_CPU_3DNOW},
	{"PFMAX",		"mmreg,r/m64",				"0F 0F /r A4",		CT_CPU_3DNOW},
	{"PFMIN",		"mmreg,r/m64",				"0F 0F /r 94",		CT_CPU_3DNOW},
	{"PFMUL",		"mmreg,r/m64",				"0F 0F /r B4",		CT_CPU_3DNOW},
	{"PFNACC",		"mmreg,r/m64",				"0F 0F /r 8A",		CT_CPU_ATHLON},
	{"PFPNACC",		"mmreg,r/m64",				"0F 0F /r 8E",		CT_CPU_ATHLON},
	{"PFRCP",		"mmreg,r/m64",				"0F 0F /r 96",		CT_CPU_3DNOW},
	{"PFRCPIT1",	"mmreg,r/m64",				"0F 0F /r A6",		CT_CPU_3DNOW},
	{"PFRCPIT2",	"mmreg,r/m64",				"0F 0F /r B6",		CT_CPU_3DNOW},
	{"PFRSQIT1",	"mmreg,r/m64",				"0F 0F /r A7",		CT_CPU_3DNOW},
	{"PFRSQRT",		"mmreg,r/m64",				"0F 0F /r 97",		CT_CPU_3DNOW},
	{"PFSUB",		"mmreg,r/m64",				"0F 0F /r 9A",		CT_CPU_3DNOW},
	{"PFSUBR",		"mmreg,r/m64",				"0F 0F /r AA",		CT_CPU_3DNOW},
	{"PI2FD",		"mmreg,r/m64",				"0F 0F /r 0D",		CT_CPU_3DNOW},
	{"PI2FW",		"mmreg,r/m64",				"0F 0F /r 0C",		CT_CPU_ATHLON},
	{"PINSRW",		"mmreg,r/m16,imm8",			"0F C4 /r ib",		CT_CPU_KATMAI},
	{"PMACHRIW",	"mmreg,mem64",				"0F 5E /r",			CT_CPU_CYRIX | CT_CPU_MMX},
	{"PMADDWD",		"mmreg,r/m64",				"0F F5 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PMAGW",		"mmreg,r/m64",				"0F 52 /r",			CT_CPU_CYRIX | CT_CPU_MMX},
	{"PMAXSW",		"mmreg,r/m64",				"0F EE /r",			CT_CPU_KATMAI},
	{"PMAXUB",		"mmreg,r/m64",				"0F DE /r",			CT_CPU_KATMAI},
	{"PMINSW",		"mmreg,r/m64",				"0F EA /r",			CT_CPU_KATMAI},
	{"PMINUB",		"mmreg,r/m64",				"0F DA /r",			CT_CPU_KATMAI},
	{"PMOVMSKB",	"reg32,mmreg",				"0F D7 /r",			CT_CPU_KATMAI},
	{"PMULHRWA",	"mmreg,r/m64",				"0F 0F /r B7",		CT_CPU_3DNOW},
	{"PMULHRWC",	"mmreg,r/m64",				"0F 59 /r",			CT_CPU_CYRIX | CT_CPU_MMX},
	{"PMULHRIW",	"mmreg,r/m64",				"0F 5D /r",			CT_CPU_CYRIX | CT_CPU_MMX},
	{"PMULHUW",		"mmreg,r/m64",				"0F E4 /r",			CT_CPU_KATMAI},
	{"PMULHW",		"mmreg,r/m64",				"0F E5 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PMULLW",		"mmreg,r/m64",				"0F D5 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PMVZB",		"mmreg,mem64",				"0F 58 /r",			CT_CPU_CYRIX | CT_CPU_MMX},
	{"PMVNZB",		"mmreg,mem64",				"0F 5A /r",			CT_CPU_CYRIX | CT_CPU_MMX},
	{"PMVLZB",		"mmreg,mem64",				"0F 5B /r",			CT_CPU_CYRIX | CT_CPU_MMX},
	{"PMVGEZB",		"mmreg,mem64",				"0F 5C /r",			CT_CPU_CYRIX | CT_CPU_MMX},
	{"POP",			"reg16",					"po 58 +r",			CT_CPU_8086},
	{"POP",			"reg32",					"po 58 +r",			CT_CPU_386},
	{"POP",			"WORD r/m16",				"po 8F /0",			CT_CPU_8086},
	{"POP",			"DWORD r/m32",				"po 8F /0",			CT_CPU_386},
//	{"POP",			"CS",						"0F",				CT_CPU_8086 | CT_CPU_UNDOC},
//	{"POP",			"DS",						"1F",				CT_CPU_8086},
//	{"POP",			"ES",						"07",				CT_CPU_8086},
//	{"POP",			"SS",						"17",				CT_CPU_8086},
//	{"POP",			"FS",						"0F A1",			CT_CPU_386},
//	{"POP",			"GS",						"0F A9",			CT_CPU_386},
	{"POPA",		"",							"61",				CT_CPU_186},
	{"POPAW",		"",							"po 61",			CT_CPU_186},
	{"POPAD",		"",							"po 61",			CT_CPU_386},
	{"POPF",		"",							"9D",				CT_CPU_186},
	{"POPFW",		"",							"po 9D",			CT_CPU_186},
	{"POPFD",		"",							"po 9D",			CT_CPU_386},
	{"POR",			"mmreg,r/m64",				"0F EB /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PREFETCH",	"mem",						"0F 0D /0",			CT_CPU_3DNOW},
	{"PREFETCHW",	"mem",						"0F 0D /1",			CT_CPU_3DNOW},
	{"PREFETCHNTA",	"mem",						"0F 18 /0",			CT_CPU_KATMAI},
	{"PREFETCHT0",	"mem",						"0F 18 /1",			CT_CPU_KATMAI},
	{"PREFETCHT1",	"mem",						"0F 18 /2",			CT_CPU_KATMAI},
	{"PREFETCHT2",	"mem",						"0F 18 /3",			CT_CPU_KATMAI},
	{"PSADBW",		"mmreg,r/m64",				"0F F6 /r",			CT_CPU_KATMAI},
	{"PSHUFW",		"mmreg,r/m64,imm8",			"0F 70 /r ib",		CT_CPU_KATMAI},
	{"PSLLW",		"mmreg,r/m64",				"0F F1 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PSLLW",		"mmreg,imm8",				"0F 71 /6 ib",		CT_CPU_PENT | CT_CPU_MMX},
	{"PSLLD",		"mmreg,r/m64",				"0F F2 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PSLLD",		"mmreg,imm8",				"0F 72 /6 ib",		CT_CPU_PENT | CT_CPU_MMX},
	{"PSLLQ",		"mmreg,r/m64",				"0F F3 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PSLLQ",		"mmreg,imm8",				"0F 73 /6 ib",		CT_CPU_PENT | CT_CPU_MMX},
	{"PSRAW",		"mmreg,r/m64",				"0F E1 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PSRAW",		"mmreg,imm8",				"0F 71 /4 ib",		CT_CPU_PENT | CT_CPU_MMX},
	{"PSRAD",		"mmreg,r/m64",				"0F E2 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PSRAD",		"mmreg,imm8",				"0F 72 /4 ib",		CT_CPU_PENT | CT_CPU_MMX},
	{"PSRLW",		"mmreg,r/m64",				"0F D1 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PSRLW",		"mmreg,imm8",				"0F 71 /2 ib",		CT_CPU_PENT | CT_CPU_MMX},
	{"PSRLD",		"mmreg,r/m64",				"0F D2 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PSRLD",		"mmreg,imm8",				"0F 72 /2 ib",		CT_CPU_PENT | CT_CPU_MMX},
	{"PSRLQ",		"mmreg,r/m64",				"0F D3 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PSRLQ",		"mmreg,imm8",				"0F 73 /2 ib",		CT_CPU_PENT | CT_CPU_MMX},
	{"PSUBB",		"mmreg,r/m64",				"0F F8 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PSUBW",		"mmreg,r/m64",				"0F F9 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PSUBD",		"mmreg,r/m64",				"0F FA /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PSUBSB",		"mmreg,r/m64",				"0F E8 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PSUBSW",		"mmreg,r/m64",				"0F E9 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PSUBUSB",		"mmreg,r/m64",				"0F D8 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PSUBUSW",		"mmreg,r/m64",				"0F D9 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PSUBSIW",		"mmreg,r/m64",				"0F 55 /r",			CT_CPU_CYRIX | CT_CPU_MMX},
	{"PSWAPD",		"mmreg,r/m64",				"0F 0F /r BB",		CT_CPU_ATHLON},
	{"PUNPCKHBW",	"mmreg,r/m64",				"0F 68 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PUNPCKHWD",	"mmreg,r/m64",				"0F 69 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PUNPCKHDQ",	"mmreg,r/m64",				"0F 6A /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PUNPCKLBW",	"mmreg,r/m64",				"0F 60 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PUNPCKLWD",	"mmreg,r/m64",				"0F 61 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PUNPCKLDQ",	"mmreg,r/m64",				"0F 62 /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"PUSH",		"reg16",					"po 50 +r",			CT_CPU_8086},
	{"PUSH",		"reg32",					"po 50 +r",			CT_CPU_386},
	{"PUSH",		"WORD r/m16",				"po FF /6",			CT_CPU_8086},
	{"PUSH",		"DWORD r/m32",				"po FF /6",			CT_CPU_386},
//	{"PUSH",		"CS",						"0E",				CT_CPU_8086},
//	{"PUSH",		"DS",						"1E",				CT_CPU_8086},
//	{"PUSH",		"ES",						"06",				CT_CPU_8086},
//	{"PUSH",		"SS",						"16",				CT_CPU_8086},
//	{"PUSH",		"FS",						"0F A0",			CT_CPU_386},
//	{"PUSH",		"GS",						"0F A8",			CT_CPU_386},
	{"PUSH",		"imm8",						"6A ib",			CT_CPU_286},
	{"PUSH",		"imm16",					"po 68 iw",			CT_CPU_286},
	{"PUSH",		"imm32",					"po 68 id",			CT_CPU_386},
	{"PUSHA",		"",							"60",				CT_CPU_186},
	{"PUSHAD",		"",							"po 60",			CT_CPU_386},
	{"PUSHAW",		"",							"po 60",			CT_CPU_186},
	{"PUSHF",		"",							"9C",				CT_CPU_186},
	{"PUSHFD",		"",							"po 9C",			CT_CPU_386},
	{"PUSHFW",		"",							"po 9C",			CT_CPU_186},
	{"PXOR",		"mmreg,r/m64",				"0F EF /r",			CT_CPU_PENT | CT_CPU_MMX},
	{"RCL",			"r/m8,1",					"D0 /2",			CT_CPU_8086},
	{"RCL",			"r/m8,CL",					"D2 /2",			CT_CPU_8086},
	{"RCL",			"r/m8,imm8",				"C0 /2 ib",			CT_CPU_286},
	{"RCL",			"r/m16,1",					"po D1 /2",			CT_CPU_8086},
	{"RCL",			"r/m16,CL",					"po D3 /2",			CT_CPU_8086},
	{"RCL",			"r/m16,imm8",				"po C1 /2 ib",		CT_CPU_286},
	{"RCL",			"r/m32,1",					"po D1 /2",			CT_CPU_386},
	{"RCL",			"r/m32,CL",					"po D3 /2",			CT_CPU_386},
	{"RCL",			"r/m32,imm8",				"po C1 /2 ib",		CT_CPU_386},
	{"RCR",			"r/m8,1",					"D0 /3",			CT_CPU_8086},
	{"RCR",			"r/m8,CL",					"D2 /3",			CT_CPU_8086},
	{"RCR",			"r/m8,imm8",				"C0 /3 ib",			CT_CPU_286},
	{"RCR",			"r/m16,1",					"po D1 /3",			CT_CPU_8086},
	{"RCR",			"r/m16,CL",					"po D3 /3",			CT_CPU_8086},
	{"RCR",			"r/m16,imm8",				"po C1 /3 ib",		CT_CPU_286},
	{"RCR",			"r/m32,1",					"po D1 /3",			CT_CPU_386},
	{"RCR",			"r/m32,CL",					"po D3 /3",			CT_CPU_386},
	{"RCR",			"r/m32,imm8",				"po C1 /3 ib",		CT_CPU_386},
	{"RCPPS",		"xmmreg,r/m128",			"0F 53 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"RCPSS",		"xmmreg,xmmreg/mem32",		"p3 0F 53 /r",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"RDMSR",		"",							"0F 32",			CT_CPU_PENT},
	{"RDPMC",		"",							"0F 33",			CT_CPU_P6},
//	{"RDSHR",		"",							"0F 36",			CT_CPU_P6 | CT_CPU_CYRIX | CT_CPU_SMM},
	{"RDTSC",		"",							"0F 31",			CT_CPU_PENT},
	{"RET",			"",							"C3",				CT_CPU_8086},
	{"RET",			"imm16",					"C2 iw",			CT_CPU_8086},
	{"RETF",		"",							"CB",				CT_CPU_8086},
	{"RETF",		"imm16",					"CA iw",			CT_CPU_8086},
	{"RETN",		"",							"C3",				CT_CPU_8086},
	{"RETN",		"imm16",					"C2 iw",			CT_CPU_8086},
	{"ROL",			"r/m8,1",					"D0 /0",			CT_CPU_8086},
	{"ROL",			"r/m8,CL",					"D2 /0",			CT_CPU_8086},
	{"ROL",			"r/m8,imm8",				"C0 /0 ib",			CT_CPU_286},
	{"ROL",			"r/m16,1",					"po D1 /0",			CT_CPU_8086},
	{"ROL",			"r/m16,CL",					"po D3 /0",			CT_CPU_8086},
	{"ROL",			"r/m16,imm8",				"po C1 /0 ib",		CT_CPU_286},
	{"ROL",			"r/m32,1",					"po D1 /0",			CT_CPU_386},
	{"ROL",			"r/m32,CL",					"po D3 /0",			CT_CPU_386},
	{"ROL",			"r/m32,imm8",				"po C1 /0 ib",		CT_CPU_386},
	{"ROR",			"r/m8,1",					"D0 /1",			CT_CPU_8086},
	{"ROR",			"r/m8,CL",					"D2 /1",			CT_CPU_8086},
	{"ROR",			"r/m8,imm8",				"C0 /1 ib",			CT_CPU_286},
	{"ROR",			"r/m16,1",					"po D1 /1",			CT_CPU_8086},
	{"ROR",			"r/m16,CL",					"po D3 /1",			CT_CPU_8086},
	{"ROR",			"r/m16,imm8",				"po C1 /1 ib",		CT_CPU_286},
	{"ROR",			"r/m32,1",					"po D1 /1",			CT_CPU_386},
	{"ROR",			"r/m32,CL",					"po D3 /1",			CT_CPU_386},
	{"ROR",			"r/m32,imm8",				"po C1 /1 ib",		CT_CPU_386},
//	{"RSDC",		"segreg,mem80",				"0F 79 /r",			CT_CPU_486 | CT_CPU_CYRIX | CT_CPU_SMM},
//	{"RSLDT",		"mem80",					"0F 7B /0",			CT_CPU_486 | CT_CPU_CYRIX | CT_CPU_SMM},
	{"RSM",			"",							"0F AA",			CT_CPU_PENT},
	{"RSQRTPS",		"xmmreg,r/m128",			"0F 52 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"RSQRTSS",		"xmmreg,r/m128",			"p3 0F 52 /r",		CT_CPU_KATMAI | CT_CPU_SSE},
//	{"RSTS",		"mem80",					"0F 7D /0",			CT_CPU_486 | CT_CPU_CYRIX | CT_CPU_SMM},
	{"SAHF",		"",							"9E",				CT_CPU_8086},
	{"SAL",			"r/m8,1",					"D0 /4",			CT_CPU_8086},
	{"SAL",			"r/m8,CL",					"D2 /4",			CT_CPU_8086},
	{"SAL",			"r/m8,imm8",				"C0 /4 ib",			CT_CPU_286},
	{"SAL",			"r/m16,1",					"po D1 /4",			CT_CPU_8086},
	{"SAL",			"r/m16,CL",					"po D3 /4",			CT_CPU_8086},
	{"SAL",			"r/m16,imm8",				"po C1 /4 ib",		CT_CPU_286},
	{"SAL",			"r/m32,1",					"po D1 /4",			CT_CPU_386},
	{"SAL",			"r/m32,CL",					"po D3 /4",			CT_CPU_386},
	{"SAL",			"r/m32,imm8",				"po C1 /4 ib",		CT_CPU_386},
	{"SAR",			"r/m8,1",					"D0 /7",			CT_CPU_8086},
	{"SAR",			"r/m8,CL",					"D2 /7",			CT_CPU_8086},
	{"SAR",			"r/m8,imm8",				"C0 /7 ib",			CT_CPU_286},
	{"SAR",			"r/m16,1",					"po D1 /7",			CT_CPU_8086},
	{"SAR",			"r/m16,CL",					"po D3 /7",			CT_CPU_8086},
	{"SAR",			"r/m16,imm8",				"po C1 /7 ib",		CT_CPU_286},
	{"SAR",			"r/m32,1",					"po D1 /7",			CT_CPU_386},
	{"SAR",			"r/m32,CL",					"po D3 /7",			CT_CPU_386},
	{"SAR",			"r/m32,imm8",				"po C1 /7 ib",		CT_CPU_386},
//	{"SALC",		"",							"D6",				CT_CPU_8086 | CT_CPU_UNDOC},
	{"SBB",			"r/m8,reg8",				"18 /r",			CT_CPU_8086},
	{"SBB",			"r/m16,reg16",				"po 19 /r",			CT_CPU_8086},
	{"SBB",			"r/m32,reg32",				"po 19 /r",			CT_CPU_386},
	{"SBB",			"reg8,r/m8",				"1A /r",			CT_CPU_8086},
	{"SBB",			"reg16,r/m16",				"po 1B /r",			CT_CPU_8086},
	{"SBB",			"reg32,r/m32",				"po 1B /r",			CT_CPU_386},
	{"SBB",			"r/m8,imm8",				"80 /3 ib",			CT_CPU_8086},
	{"SBB",			"r/m16,imm16",				"po 81 /3 iw",		CT_CPU_8086},
	{"SBB",			"r/m32,imm32",				"po 81 /3 id",		CT_CPU_386},
	{"SBB",			"r/m16,imm8",				"po 83 /3 ib",		CT_CPU_8086},
	{"SBB",			"r/m32,imm8",				"po 83 /3 ib",		CT_CPU_8086},
	{"SBB",			"AL,imm8",					"1C ib",			CT_CPU_8086},
	{"SBB",			"AX,imm16",					"po 1D iw",			CT_CPU_8086},
	{"SBB",			"EAX,imm32",				"po 1D id",			CT_CPU_386},
	{"SCASB",		"",							"AE",				CT_CPU_8086},
	{"SCASW",		"",							"po AF",			CT_CPU_8086},
	{"SCASD",		"",							"po AF",			CT_CPU_386},
	{"SETO",		"BYTE r/m8",				"0F 90 /2",			CT_CPU_386},
	{"SETNO",		"BYTE r/m8",				"0F 91 /2",			CT_CPU_386},
	{"SETB",		"BYTE r/m8",				"0F 92 /2",			CT_CPU_386},
	{"SETC",		"BYTE r/m8",				"0F 92 /2",			CT_CPU_386},
	{"SETNEA",		"BYTE r/m8",				"0F 92 /2",			CT_CPU_386},
	{"SETAE",		"BYTE r/m8",				"0F 93 /2",			CT_CPU_386},
	{"SETNB",		"BYTE r/m8",				"0F 93 /2",			CT_CPU_386},
	{"SETNC",		"BYTE r/m8",				"0F 93 /2",			CT_CPU_386},
	{"SETE",		"BYTE r/m8",				"0F 94 /2",			CT_CPU_386},
	{"SETZ",		"BYTE r/m8",				"0F 94 /2",			CT_CPU_386},
	{"SETNE",		"BYTE r/m8",				"0F 95 /2",			CT_CPU_386},
	{"SETNZ",		"BYTE r/m8",				"0F 95 /2",			CT_CPU_386},
	{"SETBE",		"BYTE r/m8",				"0F 96 /2",			CT_CPU_386},
	{"SETNA",		"BYTE r/m8",				"0F 96 /2",			CT_CPU_386},
	{"SETA",		"BYTE r/m8",				"0F 97 /2",			CT_CPU_386},
	{"SETNBE",		"BYTE r/m8",				"0F 97 /2",			CT_CPU_386},
	{"SETS",		"BYTE r/m8",				"0F 98 /2",			CT_CPU_386},
	{"SETNS",		"BYTE r/m8",				"0F 99 /2",			CT_CPU_386},
	{"SETP",		"BYTE r/m8",				"0F 9A /2",			CT_CPU_386},
	{"SETPE",		"BYTE r/m8",				"0F 9A /2",			CT_CPU_386},
	{"SETNP",		"BYTE r/m8",				"0F 9B /2",			CT_CPU_386},
	{"SETPO",		"BYTE r/m8",				"0F 9B /2",			CT_CPU_386},
	{"SETL",		"BYTE r/m8",				"0F 9C /2",			CT_CPU_386},
	{"SETNGE",		"BYTE r/m8",				"0F 9C /2",			CT_CPU_386},
	{"SETGE",		"BYTE r/m8",				"0F 9D /2",			CT_CPU_386},
	{"SETNL",		"BYTE r/m8",				"0F 9D /2",			CT_CPU_386},
	{"SETLE",		"BYTE r/m8",				"0F 9E /2",			CT_CPU_386},
	{"SETNG",		"BYTE r/m8",				"0F 9E /2",			CT_CPU_386},
	{"SETG",		"BYTE r/m8",				"0F 9F /2",			CT_CPU_386},
	{"SETNLE",		"BYTE r/m8",				"0F 9F /2",			CT_CPU_386},
	{"SFENCE",		"",							"0F AE /7",			CT_CPU_KATMAI},
//	{"SGDT",		"mem",						"0F 01 /0",			CT_CPU_286 | CT_CPU_PRIV},
//	{"SIDT",		"mem",						"0F 01 /1",			CT_CPU_286 | CT_CPU_PRIV},
//	{"SLDT",		"r/m16",					"0F 00 /0",			CT_CPU_286 | CT_CPU_PRIV},
	{"SHL",			"BYTE r/m8,1",				"D0 /4",			CT_CPU_8086},
	{"SHL",			"BYTE r/m8,CL",				"D2 /4",			CT_CPU_8086},
	{"SHL",			"BYTE r/m8,imm8",			"C0 /4 ib",			CT_CPU_286},
	{"SHL",			"WORD r/m16,1",				"po D1 /4",			CT_CPU_8086},
	{"SHL",			"WORD r/m16,CL",			"po D3 /4",			CT_CPU_8086},
	{"SHL",			"WORD r/m16,imm8",			"po C1 /4 ib",		CT_CPU_286},
	{"SHL",			"DWORD r/m32,1",			"po D1 /4",			CT_CPU_386},
	{"SHL",			"DWORD r/m32,CL",			"po D3 /4",			CT_CPU_386},
	{"SHL",			"DWORD r/m32,imm8",			"po C1 /4 ib",		CT_CPU_386},
	{"SHR",			"BYTE r/m8,1",				"D0 /5",			CT_CPU_8086},
	{"SHR",			"BYTE r/m8,CL",				"D2 /5",			CT_CPU_8086},
	{"SHR",			"BYTE r/m8,imm8",			"C0 /5 ib",			CT_CPU_286},
	{"SHR",			"WORD r/m16,1",				"po D1 /5",			CT_CPU_8086},
	{"SHR",			"WORD r/m16,CL",			"po D3 /5",			CT_CPU_8086},
	{"SHR",			"WORD r/m16,imm8",			"po C1 /5 ib",		CT_CPU_286},
	{"SHR",			"DWORD r/m32,1",			"po D1 /5",			CT_CPU_386},
	{"SHR",			"DWORD r/m32,CL",			"po D3 /5",			CT_CPU_386},
	{"SHR",			"DWORD r/m32,imm8",			"po C1 /5 ib",		CT_CPU_386},
	{"SHLD",		"WORD r/m16,reg16,imm8",	"po 0F A4 /r ib",	CT_CPU_386},
	{"SHLD",		"DWORD r/m32,reg32,imm8",	"po 0F A4 /r ib",	CT_CPU_386},
	{"SHLD",		"WORD r/m16,reg16,CL",		"po 0F A5 /r",		CT_CPU_386},
	{"SHLD",		"DWORD r/m32,reg32,CL",		"po 0F A5 /r",		CT_CPU_386},
	{"SHRD",		"WORD r/m16,reg16,imm8",	"po 0F AC /r ib",	CT_CPU_386},
	{"SHRD",		"DWORD r/m32,reg32,imm8",	"po 0F AC /r ib",	CT_CPU_386},
	{"SHRD",		"WORD r/m16,reg16,CL",		"po 0F AD /r",		CT_CPU_386},
	{"SHRD",		"DWORD r/m32,reg32,CL",		"po 0F AD /r",		CT_CPU_386},
	{"SHUFPS",		"xmmreg,r/m128,imm8",		"0F C6 /r ib",		CT_CPU_KATMAI | CT_CPU_SSE},
//	{"SMI",			"",							"F1",				CT_CPU_386 | CT_CPU_UNDOC},
	{"SMINT",		"",							"0F 38",			CT_CPU_P6 | CT_CPU_CYRIX},
	{"SMINTOLD",	"",							"0F 7E",			CT_CPU_486 | CT_CPU_CYRIX},
//	{"SMSW",		"r/m16",					"0F 01 /4",			CT_CPU_286 | CT_CPU_PRIV},
	{"SQRTPS",		"xmmreg,r/m128",			"0F 51 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"SQRTSS",		"xmmreg,xmmreg/mem32",		"p3 0F 51 /r",		CT_CPU_KATMAI | CT_CPU_SSE},
	{"STC",			"",							"F9",				CT_CPU_8086},
	{"STD",			"",							"FD",				CT_CPU_8086},
	{"STI",			"",							"FB",				CT_CPU_8086},
	{"STMXCSR",		"mem32",					"0F AE /3",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"STOSB",		"",							"AA",				CT_CPU_8086},
	{"STOSW",		"",							"po AB",			CT_CPU_8086},
	{"STOSD",		"",							"po AB",			CT_CPU_386},
//	{"STR",			"r/m16",					"0F 00 /1",			CT_CPU_286 | CT_CPU_PRIV},
	{"SUB",			"r/m8,reg8",				"28 /r",			CT_CPU_8086},
	{"SUB",			"r/m16,reg16",				"po 29 /r",			CT_CPU_8086},
	{"SUB",			"r/m32,reg32",				"po 29 /r",			CT_CPU_386},
	{"SUB",			"reg8,r/m8",				"2A /r",			CT_CPU_8086},
	{"SUB",			"reg16,r/m16",				"po 2B /r",			CT_CPU_8086},
	{"SUB",			"reg32,r/m32",				"po 2B /r",			CT_CPU_386},
	{"SUB",			"r/m8,imm8",				"80 /5 ib",			CT_CPU_8086},
	{"SUB",			"r/m16,imm16",				"po 81 /5 iw",		CT_CPU_8086},
	{"SUB",			"r/m32,imm32",				"po 81 /5 id",		CT_CPU_386},
	{"SUB",			"r/m16,imm8",				"po 83 /5 ib",		CT_CPU_8086},
	{"SUB",			"r/m32,imm8",				"po 83 /5 ib",		CT_CPU_386},
	{"SUB",			"AL,imm8",					"2C ib",			CT_CPU_8086},
	{"SUB",			"AX,imm16",					"po 2D iw",			CT_CPU_8086},
	{"SUB",			"EAX,imm32",				"po 2D id",			CT_CPU_386},
	{"SUBPS",		"xmmreg,r/m128",			"0F 5C /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"SUBSS",		"xmmreg,xmmreg/mem32",		"p3 0F 5C /r",		CT_CPU_KATMAI | CT_CPU_SSE},
//	{"SVDC",		"mem80,segreg",				"0F 78 /r",			CT_CPU_486 | CT_CPU_CYRIX | CT_CPU_SMM},
//	{"SVLDT",		"mem80",					"0F 7A /0",			CT_CPU_486 | CT_CPU_CYRIX | CT_CPU_SMM},
//	{"SVTS",		"mem80",					"0F 7C /0",			CT_CPU_486 | CT_CPU_CYRIX | CT_CPU_SMM},
//	{"SYSCALL",		"",							"0F 05",			CT_CPU_P6 | CT_CPU_AMD},
	{"SYSENTER",	"",							"0F 34",			CT_CPU_P6},
//	{"SYSEXIT",		"",							"0F 36",			CT_CPU_P6 | CT_CPU_PRIV},
//	{"SYSRET",		"",							"0F 07",			CT_CPU_P6 | CT_CPU_AMD | CT_CPU_PRIV},
	{"TEST",		"r/m8,reg8",				"84 /r",			CT_CPU_8086},
	{"TEST",		"r/m16,reg16",				"po 85 /r",			CT_CPU_8086},
	{"TEST",		"r/m32,reg32",				"po 85 /r",			CT_CPU_386},
	{"TEST",		"r/m8,imm8",				"F6 /7 ib",			CT_CPU_8086},
	{"TEST",		"r/m16,imm16",				"po F7 /7 iw",		CT_CPU_8086},
	{"TEST",		"r/m32,imm32",				"po F7 /7 id",		CT_CPU_386},
	{"TEST",		"AL,imm8",					"A8 ib",			CT_CPU_8086},
	{"TEST",		"AX,imm16",					"po A9 iw",			CT_CPU_8086},
	{"TEST",		"EAX,imm32",				"po A9 id",			CT_CPU_386},
	{"UCOMISS",		"xmmreg,xmmreg/mem32",		"0F 2E /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"UD2",			"",							"0F 0B",			CT_CPU_286},
//	{"UMOV",		"r/m8,reg8",				"0F 10 /r",			CT_CPU_386 | CT_CPU_UNDOC},
//	{"UMOV",		"r/m16,reg16",				"po 0F 11 /r",		CT_CPU_386 | CT_CPU_UNDOC},
//	{"UMOV",		"r/m32,reg32",				"po 0F 11 /r",		CT_CPU_386 | CT_CPU_UNDOC},
//	{"UMOV",		"reg8,r/m8",				"0F 12 /r",			CT_CPU_386 | CT_CPU_UNDOC},
//	{"UMOV",		"reg16,r/m16",				"po 0F 13 /r",		CT_CPU_386 | CT_CPU_UNDOC},
//	{"UMOV",		"reg32,r/m32",				"po 0F 13 /r",		CT_CPU_386 | CT_CPU_UNDOC},
	{"UNPCKHPS",	"xmmreg,r/m128",			"0F 15 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
	{"UNPCKLPS",	"xmmreg,r/m128",			"0F 14 /r",			CT_CPU_KATMAI | CT_CPU_SSE},
//	{"VERR",		"r/m16",					"0F 00 /4",			CT_CPU_286 | CT_CPU_PRIV},
//	{"VERW",		"r/m16",					"0F 00 /5",			CT_CPU_286 | CT_CPU_PRIV},
	{"WAIT",		"",							"9B",				CT_CPU_8086},
	{"WBINVD",		"",							"0F 09",			CT_CPU_486},
	{"WRMSR",		"",							"0F 30",			CT_CPU_PENT},
//	{"WRSHR",		"",							"0F 37",			CT_CPU_P6 | CT_CPU_CYRIX | CT_CPU_SMM},
	{"XADD",		"r/m8,reg8",				"0F C0 /r",			CT_CPU_486},
	{"XADD",		"r/m16,reg16",				"po 0F C1 /r",		CT_CPU_486},
	{"XADD",		"r/m32,reg32",				"po 0F C1 /r",		CT_CPU_486},
//	{"XBTS",		"reg16,r/m16",				"po 0F A6 /r",		CT_CPU_386 | CT_CPU_UNDOC},
//	{"XBTS",		"reg32,r/m32",				"po 0F A6 /r",		CT_CPU_386 | CT_CPU_UNDOC},
	{"XCHG",		"reg8,r/m8",				"86 /r",			CT_CPU_8086},
	{"XCHG",		"reg16,r/m8",				"po 87 /r",			CT_CPU_8086},
	{"XCHG",		"reg32,r/m32",				"po 87 /r",			CT_CPU_386},
	{"XCHG",		"r/m8,reg8",				"86 /r",			CT_CPU_8086},
	{"XCHG",		"r/m16,reg16",				"po 87 /r",			CT_CPU_8086},
	{"XCHG",		"r/m32,reg32",				"po 87 /r",			CT_CPU_386},
	{"XCHG",		"AX,reg16",					"po 90 +r",			CT_CPU_8086},
	{"XCHG",		"EAX,reg32",				"po 90 +r",			CT_CPU_386},
	{"XCHG",		"reg16,AX",					"po 90 +r",			CT_CPU_8086},
	{"XCHG",		"reg32,EAX",				"po 90 +r",			CT_CPU_386},
	{"XLATB",		"",							"D7",				CT_CPU_8086},
	{"XOR",			"r/m8,reg8",				"30 /r",			CT_CPU_8086},
	{"XOR",			"r/m16,reg16",				"po 31 /r",			CT_CPU_8086},
	{"XOR",			"r/m32,reg32",				"po 31 /r",			CT_CPU_386},
	{"XOR",			"reg8,r/m8",				"32 /r",			CT_CPU_8086},
	{"XOR",			"reg16,r/m16",				"po 33 /r",			CT_CPU_8086},
	{"XOR",			"reg32,r/m32",				"po 33 /r",			CT_CPU_386},
	{"XOR",			"r/m8,imm8",				"80 /6 ib",			CT_CPU_8086},
	{"XOR",			"r/m16,imm16",				"po 81 /6 iw",		CT_CPU_8086},
	{"XOR",			"r/m32,imm32",				"po 81 /6 id",		CT_CPU_386},
	{"XOR",			"r/m16,imm8",				"po 83 /6 ib",		CT_CPU_8086},
	{"XOR",			"r/m32,imm8",				"po 83 /6 ib",		CT_CPU_386},
	{"XOR",			"AL,imm8",					"34 ib",			CT_CPU_8086},
	{"XOR",			"AX,imm16",					"po 35 iw",			CT_CPU_8086},
	{"XOR",			"EAX,imm32",				"po 35 id",			CT_CPU_386},
	{"XORPS",		"xmmreg,r/m128",			"0F 57 /r",			CT_CPU_KATMAI | CT_CPU_SSE}
};


static int cinstset_compare_syntax(const void *element1, const void *element2)
{
	return stricmp(((CInstSyntax*)element1)->mnemonic, 
		((CInstSyntax*)element2)->mnemonic);
}

static int cinstset_compare_entry(const void *mnemonic, const void *entry)
{
	return stricmp((char*)mnemonic, ((CInstructionEntry*)entry)->mnemonic);
}

int cinstset_num_instructions(void)
{
	return sizeof(cinstruction_set) / sizeof(CInstSyntax);
}

int cinstset_num_mnemonics(void)
{
	static int num = 0;
	int i;
	if (!num) {
		if (cinstset_num_instructions() != 0) {
			num = 1;
		}
		for(i = 0; i + 1 < cinstset_num_instructions(); i++) {
			if (stricmp(cinstruction_set[i].mnemonic, 
				cinstruction_set[i + 1].mnemonic) != 0) {
				num++;
			}
		}
	}

	return num;
}

static void cinstset_matrix_sort(void)
{
	static int inited = 0;
	if (inited == 0) {
		inited = 1;
		qsort(cinstruction_set, cinstset_num_instructions(), 
			sizeof(CInstSyntax), cinstset_compare_syntax);
	}
}

CInstructionSet *cinstset_create(void)
{
	CInstructionSet *self;
	int i, j;

	cinstset_matrix_sort();

	self = (CInstructionSet*)malloc(sizeof(CInstructionSet));
	assert(self);

	self->instructionMap = (CInstructionEntry*)malloc(
		sizeof(CInstructionEntry) * cinstset_num_mnemonics());

	for (i = 0, j = 0; i < cinstset_num_instructions(); ) {
		self->instructionMap[j].mnemonic = cinstruction_set[i].mnemonic;
		self->instructionMap[j].instruction = 
			cinst_create(&cinstruction_set[i++]);

		while (i < cinstset_num_instructions() && 
			stricmp(cinstruction_set[i - 1].mnemonic, 
			cinstruction_set[i].mnemonic) == 0) {
			cinst_attach_new(self->instructionMap[j].instruction, 
				&cinstruction_set[i++]);
		}

		j++;
	}
	assert(j == cinstset_num_mnemonics());
	return self;
}

void cinstset_release(CInstructionSet *self)
{
	int i;
	assert(self);
	for (i = 0; i < cinstset_num_mnemonics(); i++) {
		cinst_release(self->instructionMap[i].instruction);
	}
	free(self->instructionMap);
	self->instructionMap = NULL;
	free(self);
}


CInstruction *cinstset_query(const CInstructionSet *self, const char *name)
{
	CInstructionEntry *entry;
	assert(self && name);
	assert(self->instructionMap);

	entry = (CInstructionEntry*)bsearch(name, self->instructionMap, 
		cinstset_num_mnemonics(), sizeof(CInstructionEntry), 
		cinstset_compare_entry);

	if (entry == NULL) {
		fprintf(stderr, "Unrecognised mnemonic '%s'\n", name);
		fflush(stderr);
		return NULL;
	}

	cinst_reset_match(entry->instruction);

	return entry->instruction;
}


